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W78L32 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78L32 microcontroller supplies a wider frequency range and supply voltages than most 8-bit microcontrollers on the market. It is compatible with the industry standard 80C32 microcontroller series. The W78L32 contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters and a serial port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256 bytes of RAM, and the device supports ROMless operation for application programs. The W78L32 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
FEATURES
* Fully static design * Supply voltage of 1.8V to 5.5V * Low power consumption at full supply voltage * DC-24 MHz operation * 256 bytes of on-chip scratchpad RAM * 64K bytes program memory address space * 64K bytes data memory address space * Four 8-bit bidirectional ports * Three 16-bit timer/counters * One full duplex serial port * Boolean processor * Six-source, two-level interrupt capability * Built-in power management * Packages:
- DIP 40: W78L32-24 - PLCC 44: W78L32P-24 - QFP 44: W78L32F-24
-1-
Publication Release Date: September 1998 Revision A1
W78L32
PIN CONFIGURATIONS
40-Pin DIP (W78L32)
T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8
44-Pin PLCC (W78L32P)
44-Pin QFP (W78L32F)
T 2 E X , PPPP 1111 .... 4321
T 2 E X , PPPP 1111 .... 4321
A T D 2 0 , , P P 1 V0 . ND. 0 CD0
A D 1 , P 0 . 1
A D 2 , P 0 . 2
A D 3 , P 0 . 3
T 2 , P 1 V . ND 0 CD
A D 0 , P 0 . 0
A D 1 , P 0 . 1
A D 2 , P 0 . 2
A D 3 , P 0 . 3
P1.5 P1.6 P1.7 RST RXD, P3.0 NC TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVNP TSC2 . AS L 0 , 1 A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA NC ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
P1.5 P1.6 P1.7 RST RXD, P3.0 NC TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
1 2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X VN P T SC 2 AS . L 0 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA NC ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
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W78L32
PIN DESCRIPTION
P0.0-P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory.
P1.0-P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0-P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.
P3.0-P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate functions, which are described below: PIN P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 ALTERNATE FUNCTION RXD Serial Receive Data TXD Serial Transmit Data INT0 External Interrupt 0 INT1 External Interrupt 1 T0 Timer 0 Input T1 Timer 1 Input WR Data Write Strobe RD Data Read Strobe
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM. This pin should be kept low for all W78L32 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor.
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high state during reset with a weak pull-up.
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Publication Release Date: September 1998 Revision A1
W78L32
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0 address/data bus during fetch and MOVC operations. PSEN goes to a high state during reset with a weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VDD
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
RAM 256 Bytes
SFR Port 0 Port 1 Alternate Timer 2
CPU CORE
Data Bus
Port 2 Port 3 Alternate Serial Port Timer 0 Interrupt Timer 1 INT 0 INT 1 Watchdog Timer
-4-
W78L32
FUNCTIONAL DESCRIPTION
The W78L32 architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different instruction and references both a 64K program address space and a 64K data storage space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature of the W78L32: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
Clock
The W78L32 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78L32 relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78L32 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts when VDD = 5V.
Power Management
Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a reset.
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Publication Release Date: September 1998 Revision A1
W78L32
Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L32 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VCC-VSS VIN TA TST MIN. -0.3 VSS -0.3 0 -55 MAX. +7.0 VCC +0.3 70 +150 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC CHARACTERISTICS
(VDD-VSS = 5V 10%, TA = 25C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3 Input Current RST Input Leakage Current P0, EA Logic 1 to 0 Transition Current P1, P2, P3
SYM. VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL [*4]
PECIFICATION MIN. 1.8 -50 -10 -10 -500 MAX. 5.5 20 3 6 1.5 50 20 +10 +300 +10 -
UNIT V mA mA mA mA A A A A A A
TEST CONDITIONS
No load, VDD = 5.5V, 20 MHz No load, VDD = 2.0V, 16 MHz VDD = 5.5V, Fosc = 20 MHz VDD = 2.0V, Fosc =16 MHz VDD = 5.5V, Fosc = 20 MHz VDD = 2.0V, Fosc = 16 MHz VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0V < VIN < VDD VDD = 5.5V VIN = 2.0V
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W78L32
DC Characteristics, continued
PARAMETER Input Low Voltage P0, P1, P2, P3, EA Input Low Voltage RST Input Low Voltage XTAL1 [*4] Input High Voltage P0, P1, P2, P3, EA Input High Voltage RST Input High Voltage XTAL1 [*4] Output Low Voltage P1, P2, P3 Output Low Voltage P0, ALE, PSEN [*3] Sink Current P1, P2, P3 Sink Current P0, ALE, PSEN Output High Voltage P1, P2, P3 Output High Voltage P0, ALE, PSEN [*3] Source Current P1, P2, P3 Source Current P0, ALE, PSEN
Notes:
SYM. VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 VOL1 VOL2 ISK1 ISK2 VOH1 VOH2
PECIFICATION MIN. 0 0 0 0 0 0 2.4 1.4 3.5 1.7 3.5 1.6 4 1.8 8 4.5 2.4 1.4 2.4 1.4 MAX. 0.8 0.5 0.8 0.3 0.8 0.6 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 0.45 0.25 0.45 0.25 9 5.4 16 9 -250 -30 -16 -2.4
UNIT V V V V V V V V V V V V V V V V mA mA mA mA V V V V A A mA mA
TEST CONDITIONS VDD = 4.5V VDD = 2.0V VDD = 4.5V VDD = 2.0V VDD = 4.5V VDD = 2.0V VDD = 5.5V VDD = 2.0V VDD = 5.5V VDD = 2.0V VDD = 5.5V VDD = 2.0V VDD = 4.5V, IOL = +2 mA VDD = 2.0V, IOL = +1 mA VDD = 4.5V, IOL = +4 mA VDD = 2.0V, IOL = +2 mA VDD = 4.5V, Vin = 0.45V VDD = 2.0V, Vin = 0.45V VDD = 4.5V, Vin = 0.45V VDD = 2.0V, Vin = 0.45V VDD = 4.5V, IOH = -100 A VDD = 2.0V, IOH = -8 A VDD = 4.5V, IOH = -400 A VDD = 2.0V,IOH = -200 A VDD = 4.5V,Vin = 2.4V VDD = 2.0V,Vin = 1.4V VDD = 4.5V,Vin = 2.4V VDD = 2.0V,Vin = 1.4V
ISR1 ISR2
-100 -12 -8 -1.4
*1. RST pin is a Schmitt trigger input. *3. P0, ALE and /PSEN are tested in the external access mode. *4. XTAL1 is a CMOS input. *5. Pins of P1, P2, P3 can source a transition current when they are being externally driven from 1 to 0.
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Publication Release Date: September 1998 Revision A1
W78L32
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 nS variation. The numbers below represent the performance expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
T CH F OP, TCP TCL
PARAMETER Operating Speed Clock Period Clock High Clock Low
SYMBOL FOP TCP TCH TCL
MIN. 0 25 10 10
TYP. -
MAX. 24 -
UNIT MHz nS nS nS
NOTES 1 2 3 3
Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER Address Valid to ALE Low Address Hold after ALE Low ALE Low to PSEN Low PSEN Low to Data Valid Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width SYMBOL TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW MIN. 1 TCP- 1 TCP- 1 TCP- 0 0 2 TCP- 3 TCP- TYP. 2 TCP 3 TCP MAX. 2 TCP 1 TCP 1 TCP UNIT nS nS nS nS nS nS nS nS 4 4 NOTES 4 1, 4 4 2 3
PSEN Pulse Width
Notes: 1. P0.0-P0.7, P2.0-P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "" ( due to buffer driving delay and wire loading) is 20 nS.
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W78L32
Data Read Cycle
PARAMETER ALE Low to RD Low RD Low to Data Valid Data Hold after RD High Data Float after RD High RD Pulse Width SYMBOL TDAR TDDA TDDH TDDZ TDRD MIN. 3 TCP- 0 0 6 TCP- TYP. 6 TCP MAX. 3 TCP+ 4 TCP 2 TCP 2 TCP UNIT nS nS nS nS nS 2 NOTES 1, 2 1
Notes: 1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER ALE Low to WR Low Data Valid to WR Low Data Hold from WR High WR Pulse Width SYMBOL TDAW TDAD TDWD TDWR MIN. 3 TCP- 1 TCP- 1 TCP- 6 TCP- TYP. 6 TCP MAX. 3 TCP+ UNIT nS nS nS nS
Note: "" ( due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE SYMBOL TPDS TPDH TPDA MIN. 1 TCP 0 1 TCP TYP. MAX. UNIT nS nS nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference.
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Publication Release Date: September 1998 Revision A1
W78L32
TIMING WAVEFORMS
Program Fetch Cycle
S1 XTAL1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
TALW ALE TAPL PSEN TPSW TAAS PORT 2 TAAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 TPDA TPDH, TPDZ
Data Read Cycle
S4 XTAL1 ALE PSEN PORT 2
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA T DAR T DDA
PORT 0 T DDH, T DDZ RD T DRD
- 10 -
W78L32
Timing Waveforms, continued
Data Write Cycle
S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA OUT
TDAD
TDWD
TDAW
TDWR
Port Access Cycle
S5 XTAL1
S6
S1
ALE T PDS PORT INPUT SAMPLE T PDH T PDA DATA OUT
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Publication Release Date: September 1998 Revision A1
W78L32
TYPICAL APPLICATION CIRCUITS
Using External Program Memory and Crystal
VDD
31 19 10 u R
CRYSTAL
EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78L32
18 9
8.2 K C1 C2
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND
3 4 7 8 13 14 17 18 1 11
D0 D1 D2 D3 D4 D5 D6 D7 OC G
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
12 13 14 15 1 2 3 4 5 6 7 8
74LS373
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 GND
10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 20 22
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE 27512
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Figure A
CRYSTAL 16 MHz 24 MHz 33 MHz 40 MHz
C1 30P 15P 10P 5P
C2 30P 15P 10P 5P
R 6.8K 4.7K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
- 12 -
W78L32
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
V DD
31 19 10 u
OSCILLATOR
EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78L32
18 8.2 K 9 12 13 14 15 1 2 3 4 5 6 7 8
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14
AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1 11
D0 D1 D2 D3 D4 D5 D6 D7 OC G
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
74LS373
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND
10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 22 27
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WR 20256
D0 D1 D2 D3 D4 D5 D6 D7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Figure B
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Publication Release Date: September 1998 Revision A1
W78L32
PACKAGE DIMENSIONS
40-pin DIP
Symbol
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15 0.670 0.090 14.986 13.72 2.286 3.048 0 16.00 16.51 0.254 3.81 0.406 1.219 0.203 3.937 0.457 1.27 0.254 52.20 15.24 13.84 2.54 3.302 4.064 0.559 1.372 0.356 52.58 15.494 13.97 2.794 3.556 15 17.01 2.286 5.334
D 40 21
E1
A A1 A2 B B1 c D E E1 e1 L
a
1
20 E c
eA S
Notes:
S
A A2
A1
Base Plane Seating Plane
L B B1
e1
a
eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
44-pin PLCC
HD D
6 1 44 40
Symbol
7 39
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.185 0.020 0.145 0.026 0.016 0.008 0.648 0.648 0.150 0.028 0.018 0.010 0.653 0.653 0.155 0.032 0.022 0.014 0.658 0.658 0.508 3.683 0.66 0.406 0.203 16.46 16.46 3.81 0.711 0.457 0.254 16.59 16.59 3.937 0.813 0.559 0.356 16.71 16.71 4.699
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.050 0.590 0.590 0.680 0.680 0.090
BSC 0.630 0.630 0.700 0.700 0.110 0.004
1.27 14.99 14.99 17.27 17.27 2.296
BSC 16.00 16.00 17.78 17.78 2.794 0.10
0.610 0.610 0.690 0.690 0.100
15.49 15.49 17.53 17.53 2.54
L A2 A
e
Seating Plane GD
b b1
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
- 14 -
W78L32
Package Dimensions, continued
44-pin QFP
HD D
Dimension in inch
Dimension in mm
Symbol
44 34
Min. Nom. Max.
--0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7
Min. Nom.
--0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6
Max.
--0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08
1
33
E HE
11
12
e
b
22
A A1 A2 b c D E e HD HE L L1 y
Notes:
c
0
7
A2 A A1 L L1 Detail F
Seating Plane
See Detail F
y
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec.
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 15 -
Publication Release Date: September 1998 Revision A1

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